Use of CAS signal in 8259A PIC Cascading

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As far as I understand, the 8259A Cascading works in the following procedures:

  • slave 8259A raises a interrupt to master 8259A (e.g. through IR0)
  • processor ‘calls’ INTA pin on master 8259A
  • master set the INT pin high to notify the processor of an interrupt and that the interrupt is from a slave 8259A
  • the processor read slave 8259A’s IO port to get the interrupt vector

My question is that since the processor can directly read/write the slave’s I/O port, and none of the other 8259As will do read/write because their CS (chip select) is not activated (address on bus do not match their I/O ports), then why CAS signal between the master and the slaves is necessary? i.e. Each slaves can ‘know’ if they are communicating with the processor without reading CAS signal.

FYI:

8259A casecade

description from the datasheet:

CASCADE LINES:The CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins are outputs for a master 8259Aand inputs for a slave 8259A

I’m not sure if there’s something wrong with my understanding, and this problem has troubled me for a long time.

Thanks in advance for any help.

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